A processor does not execute a program as one large operation. A program is divided into individual machine instructions, and the CPU processes those instructions one at a time through a controlled sequence of activities. This sequence is called the instruction cycle.
The instruction cycle explains what happens inside a CPU after an instruction has been placed in memory. The processor must first locate the instruction, bring it into the CPU, determine what the instruction means, obtain any required operands, perform the requested operation, and place the result where it is needed. These activities are coordinated by the control unit and supported by CPU registers, the ALU, memory, and the system buses.
The exact implementation differs between processor architectures, but the basic idea remains important in Computer Organization: the CPU repeatedly obtains instructions, interprets them, and carries out their operations.
An instruction is a machine-level command that tells the processor to perform a particular operation. Depending on the instruction set architecture, an instruction may perform arithmetic, move data, compare values, access memory, or change the normal sequence of program execution.
An instruction generally contains an opcode and information about its operands. The opcode identifies the operation, while operand information identifies the data, registers, memory locations, or immediate values involved in that operation.
ADD R1, R2, R3 ADD → operation to perform R1 → destination register R2 → first source register R3 → second source register Meaning: R1 = R2 + R3
The actual binary encoding of this instruction depends on the processor's instruction set. The CPU does not directly execute the textual form ADD R1, R2, R3; that notation is a human-readable representation of the machine instruction.
The instruction cycle is the sequence of operations performed by the CPU to process an instruction. At a simplified level, it can be represented as:
┌───────────────┐
│ Fetch │
└───────┬───────┘
↓
┌───────────────┐
│ Decode │
└───────┬───────┘
↓
┌────────────────────┐
│ Fetch Operands │
│ if required │
└─────────┬──────────┘
↓
┌───────────────┐
│ Execute │
└───────┬───────┘
↓
┌────────────────┐
│ Write Result │
│ if required │
└───────┬────────┘
↓
┌────────────────┐
│ Next Instruction│
└────────────────┘
Not every instruction requires every stage in exactly the same form. For example, an instruction that adds two registers does not need to read an operand from main memory, while a load instruction must access memory. Similarly, some instructions do not produce a conventional arithmetic result that needs to be written back.
The fetch stage begins the processing of an instruction. The CPU needs to determine the memory location containing the next instruction. The Program Counter (PC) normally contains this address.
The address from the PC is used to access memory. The instruction stored at that location is transferred toward the processor and loaded into the Instruction Register (IR). The PC is then normally advanced so that it points to the following instruction.
The exact hardware sequence varies between processors, but a simplified traditional sequence can be represented using the MAR and MDR:
PC → MAR Memory[MAR] → MDR MDR → IR PC → address of next instruction
The important idea is that the CPU obtains the next instruction from the location identified by the program counter and places the instruction in a register where the control logic can interpret it.
After the instruction reaches the Instruction Register, the CPU must determine what it represents. This activity is called instruction decoding.
The control unit examines the instruction's opcode and other fields. From these fields, the processor determines the operation to perform, the registers or memory locations involved, and the type of operand access required.
For example, if the instruction represents an addition between two registers, the control logic must arrange for the appropriate register values to reach the ALU and select addition as the required ALU operation.
Instruction Register
↓
Instruction
Decoder
↓
┌───────────────┐
│ Operation │
│ Operand info │
│ Control needs │
└───────────────┘
↓
Control Signals
The decoder therefore acts as an important bridge between the binary instruction and the hardware actions required to execute it.
Once the CPU understands the instruction, it determines where the required operands are located. Depending on the instruction, operands may already be available in registers, may be included directly within the instruction, or may need to be obtained from memory.
For a register-to-register operation, the CPU can obtain the operands from its internal registers. For a memory-access instruction, the processor must calculate or obtain the required address and communicate with memory.
Instruction: ADD R1, R2, R3 R2 = 25 R3 = 15 Operands required: 25 and 15 Both values are already in CPU registers.
Instruction: LOAD R1, [5000] Meaning: Read the value stored at memory address 5000 and place that value into R1.
This stage is therefore conditional. The processor performs additional memory access when the instruction requires it; it does not need to fetch every operand from main memory.
During the execute stage, the CPU performs the operation specified by the instruction. The exact activity depends on the instruction type.
Arithmetic and logical instructions commonly use the Arithmetic Logic Unit (ALU). Other instructions may perform data movement, memory access, comparison, bit manipulation, or control-flow operations.
R2 = 25 R3 = 15 Instruction: ADD R1, R2, R3 ALU operation: 25 + 15 = 40 Result: R1 = 40
For a branch instruction, execution may instead involve evaluating a condition and changing the program counter. This demonstrates why the execute stage cannot be reduced only to arithmetic calculations.
When an instruction produces a result, the processor must place that result in its intended destination. This activity is commonly called the write-back stage.
The destination may be a CPU register, a memory location, or another processor-defined destination depending on the instruction.
Before execution: R2 = 25 R3 = 15 Instruction: ADD R1, R2, R3 Execution: 25 + 15 = 40 Write-back: R1 = 40
Not every instruction has a separate write-back operation. For example, a store instruction writes data to memory, while a branch instruction primarily changes the flow of execution.
Several CPU registers participate in the traditional explanation of instruction processing. Their names and exact behavior can differ between architectures, but they provide a useful model for understanding how information moves through the processor.
| Register | Primary Purpose |
|---|---|
| Program Counter (PC) | Holds the address associated with the next instruction to be fetched. |
| Instruction Register (IR) | Holds the instruction currently being interpreted or executed. |
| Memory Address Register (MAR) | In traditional CPU models, holds the memory address involved in a memory operation. |
| Memory Data Register (MDR) | In traditional CPU models, temporarily holds data or an instruction transferred to or from memory. |
| General-Purpose Registers | Hold operands, addresses, intermediate values, and results according to the instruction set. |
The MAR and MDR are especially common in introductory Computer Organization diagrams. Modern processors may implement memory operations internally using considerably more complex structures, so these registers should be understood as a useful conceptual model rather than a description of every modern CPU's physical implementation.
Consider a simplified three-address instruction:
ADD R1, R2, R3
Assume:
R2 = 120 R3 = 80
A simplified instruction-processing sequence is:
FETCH PC identifies the address of the ADD instruction. The instruction is read from memory. The instruction is placed in IR. PC advances toward the next instruction. DECODE Control logic identifies the operation as ADD. Source registers are identified as R2 and R3. Destination register is identified as R1. OPERAND ACCESS R2 supplies 120. R3 supplies 80. EXECUTE ALU performs: 120 + 80 = 200 WRITE-BACK Result is written to R1. R1 = 200
The next instruction can then be fetched. This repeated process allows the processor to execute an entire program instruction by instruction.
The normal sequential flow of a program can be changed by instructions such as conditional branches, jumps, calls, and returns. These instructions are important because the next instruction is not always simply the instruction immediately following the current one in memory.
For example, consider a conditional branch:
BEQ R1, R2, 5000
A simplified interpretation is:
Compare R1 and R2
If they are equal:
PC ← 5000
Otherwise:
continue with the normal next instruction
This is why the Program Counter is more accurately understood as the register controlling the location of the next instruction to be fetched, rather than simply a counter that always increases by one.
CPU operations are coordinated with timing signals. A processor's control logic uses clock events to organize internal activities and ensure that data moves through the appropriate hardware at the appropriate time.
It is important, however, not to assume that one complete instruction always requires exactly one clock cycle. In real processors, an instruction may require multiple internal steps, and different instructions may take different amounts of work. Modern processors can also overlap the processing of several instructions using techniques such as pipelining.
Therefore, instruction cycle and clock cycle are related concepts, but they are not necessarily identical.
| Term | Meaning |
|---|---|
| Clock Cycle | A timing interval defined by the processor's clock. |
| Machine Cycle | A term traditionally used for a basic hardware operation or bus-level activity, depending on the processor architecture. |
| Instruction Cycle | The complete sequence of activities required to process one instruction. |
These terms are sometimes used differently in different textbooks and processor architectures. When studying for an examination, it is therefore useful to follow the terminology used by the particular syllabus or processor being discussed.
An interrupt allows hardware or software to request the processor's attention. Interrupt processing is related to the instruction cycle because the CPU must determine an appropriate point at which it can respond to an interrupt.
In a simplified processor model, after completing an instruction, the CPU may check whether an interrupt request needs to be serviced. If an appropriate interrupt is pending and enabled, the processor saves the necessary execution state and transfers control to an interrupt service routine.
Execute current instruction
↓
Check for interrupt
↓
┌────┴────┐
↓ ↓
No request Request
↓ ↓
Fetch next Save required state
instruction ↓
Run handler
↓
Resume program
The exact interrupt mechanism varies considerably between processor architectures, but the basic concept connects instruction execution with event handling.
The fetch-decode-execute model is extremely useful for learning CPU organization, but modern processors are considerably more sophisticated than this simplified sequence suggests.
A modern processor may use instruction pipelines, multiple execution units, branch prediction, caching, out-of-order execution, register renaming, and other techniques to improve throughput. As a result, several instructions can be in different stages of processing at the same time.
For example, while one instruction is being executed, another may be decoded and another may be fetched. This does not mean that the basic instruction-processing concept has disappeared. Instead, the processor has been designed to overlap and optimize the individual activities.
The simplified instruction cycle should therefore be viewed as a foundation for understanding more advanced processor organization.
Suppose a high-level language contains an expression such as:
total = price + tax;
A compiler may translate this operation into one or more machine instructions. A simplified processor might eventually execute operations resembling:
LOAD R2, price LOAD R3, tax ADD R1, R2, R3 STORE total, R1
Each machine instruction then goes through the processor's instruction-processing mechanism. The CPU does not understand the original high-level statement directly; it executes the machine-level instructions produced by the compiler or other software tools.
This example illustrates an important relationship between software and hardware: a high-level operation may result in several machine instructions, and each machine instruction must be processed by the processor according to the rules of its instruction set architecture.
| Misconception | Correct Understanding |
|---|---|
| Every instruction always requires a memory access to obtain its operands. | Operands may already be in registers or may be encoded directly in the instruction. Memory access is required only when the instruction needs it. |
| Every instruction performs an arithmetic operation. | Instructions can also transfer data, compare values, access memory, manipulate bits, or change program flow. |
| The PC always increases after every instruction. | The PC normally advances during sequential execution, but branch, jump, call, return, exception, and interrupt mechanisms can change its value. |
| One instruction always takes exactly one clock cycle. | The number of clock cycles and internal operations depends on the processor architecture and instruction. |
| The instruction cycle is identical in every CPU. | The fundamental idea is common, but the actual implementation differs across instruction set architectures and processor designs. |
The instruction cycle provides a framework for connecting several important Computer Organization concepts. The Program Counter explains how the processor identifies the next instruction, the Instruction Register holds the current instruction, the control unit interprets it, registers supply or receive values, the ALU performs many computational operations, and memory provides instructions and data when required.
Once this sequence is understood, topics such as instruction formats, addressing modes, CPU architecture, pipelining, interrupts, cache memory, and processor performance become easier to study because they can be related back to the basic process of executing instructions.
The instruction cycle describes how a processor turns a machine instruction into a completed operation. The CPU first identifies and fetches an instruction, places it where the control logic can interpret it, determines the required operands and operation, performs the requested work, and stores any resulting value in the appropriate destination.
Registers such as the PC and IR are central to this process, while registers such as the MAR and MDR provide a useful traditional model for understanding communication with memory. The ALU handles many arithmetic and logical operations, while the control unit coordinates the activities required to execute the instruction.
The simplified fetch-decode-execute model is the foundation for understanding processor operation. Real CPUs add sophisticated mechanisms such as pipelining, caching, branch prediction, and multiple execution units, but these technologies build upon the same fundamental idea of processing machine instructions.